The present invention relates to a method for fabricating a semiconductor memory device and a structure thereof, and more particularly to a method for fabricating non-volatile semiconductor memory devices having a storage cell array including therein Electrically Programmable Read Only Memory (hereinafter referred to as EPROM) or Electrically Erasable and Programmable Read Only Memory (hereinafter referred to as EEPROM) and having a peripheral circuit which consists of MOS transistors, and to a structure thereof.
Among non-volatile semiconductor memory devices, EPROM and EEPROM devices have a floating gate and a control gate deposited on a semiconductor substrate having a source and a drain thereon. Basic structures of the EPROM and EEPROM are disclosed in U.S. Pat. No. 3,500,142.
In general, as disclosed in the aforesaid U.S. patent, an EPROM is programmed by injecting hot electrons to floating gates from channel area and the program is erased by exposing the memory device under ultra-violet rays. Likewise, the EEPROM is programmed by tunneling of electrons from drain area to floating gates and the program is erased by tunneling of electrons from the floating gates to the drain area. Here, the capacitance required for programming operation of EPROM, or programming or erasing operation of EEPROM, is secured by an insulation layer formed between the floating gate and the control gate above the floating gate.
In case of EEPROM, for example, programming or writing operation is performed by tunneling of electrons from a drain to a floating gate by applying a high voltage and a ground voltage to the control gate and the drain, respectively, and floating the source, while erasing or reading operation is performed by tunneling of electrons from the floating gate to the drain by applying a high voltage to the drain, and grounding the control gate while the source is in floating state. In programming, a voltage between a floating gate and a substrate can be described by the following expression: ##EQU1## wherein a voltage applied to the control gate is represented by V.sub.pp, a capacitance between the control gate and a floating gate is represented by C.sub.1, a capacitance between the floating gate and a substrate is represented by C.sub.2, a voltage between the floating gate and the substrate is represented by V.sub.FG. Here, the larger the V.sub.FG is, the stronger electric field is induced between the floating gate and the substrate, and accordingly the tunneling characteristics of electrons is improved. Hence, in order to improve the tunneling effect of electrons, value of the V.sub.FG needs to be increased. As obvious from the expression (1), increase of the capacitance C.sub.1 between the control gate and the floating gate is required to increase the value of V.sub.FG in a given voltage V.sub.pp. However, since semiconductor devices are nowadays in tendency of getting more highly integrated and becoming smaller and smaller, which inevitably leads to more reduced space for containing the semiconductor, it is necessary to find a solution to overcome decrease of capacitance caused by such reduced space of cell occupation in a semiconductor device having storage cell array, which consists of floating gate memory, and peripheral circuits.
As a way to bring the solution, it has been proposed to use O--N--O (Oxide-Nitride-Oxide) layer, which has a greater permittivity than silicon oxide layer, for forming an insulation layer between the floating gate and the control gate. Here, permittivity of the oxide layer is .epsilon..sub.ox .apprxeq.3.9 and permittivity of the O--N--O layer is .epsilon..sub.sin .apprxeq.7.5. Therefore, the O--N--O insulation can achieve a capacitance of about twice as much as that in the oxide layer insulation, in accordance with the following expression: ##EQU2## when the two layers have the same thickness (t) of insulation layer. Another proposal is to increase area of a capacitor to achieve larger capacitance.
FIGS. 1A through 1E, as disclosed in U.S. Pat. No. 4,697,330, illustrate a part of fabrication process of a non-volatile semiconductor memory device having storage cell array and peripheral circuit according to a prior art. As shown in the figures, a semiconductor substrate 10 has a storage cell area 35 and a peripheral circuit area 40. As illustrated in FIG. 1A, after forming field oxide layer 12 on the semiconductor substrate 10 by employing a known local oxidation, a gate insulation layer 14 is formed on the semiconductor substrate 10. And a first polycrystalline silicon layer 16, a first oxide layer 18 made of silicon oxide (SiO.sub.2), a first nitride layer 20 made of silicon nitride (Si.sub.3 N.sub.4) and a first photo-resist layer 22 are sequentially formed on the substrate 10, and a given mask pattern is formed thereon. Then, by a local etching process, a floating gate 16 of the storage cell area 35 is formed. The upper surface of the field oxide layer 12 and the bulk silicon substrate 10 of the peripheral circuit area 40 are exposed by this local etching.
As shown in FIG. 1B, after the photo-resist layer 22 is removed, a second oxide layer 26 made of silicon oxide layer is formed on the upper surface of the O--N layer over the storage cell area 35 and the upper surface of the exposed bulk silicon substrate 10 of the peripheral circuit area 40 by employing thermal oxidation method or oxide deposition. The second oxide layer 26, which is formed on the bulk silicon substrate 10, serves as a gate insulation layer for a MOS transistor of the peripheral area 40. On the other hand, when the second oxide layer 26 is being formed, a first polycrystalline silicon oxide layer 27 is formed onto the side of the floating gate 16 due to a sort of reaction between polycrystalline silicon exposed in the side of the floating gate 16 and the second oxide layer. Thereafter, a second polycrystalline silicon layer 28 is formed on the top surface of the bulk silicon substrate 10.
As illustrated in FIG. 1C, a second photo-resist layer 30 is coated on the second polycrystalline silicon layer 28. And, after a mask pattern of the second photo-resist layer is formed, a control gate is etched so as to complete formation of a cell array of the storage cell area 35.
Then, the second photo-resist layer 30 is removed, and a pattern is formed after coating a third photo-resist layer 32 on the entire surface of the substrate 10 so as to complete formation of a gate 33 of the MOS transistor of the peripheral circuit area 40, as illustrated in FIG. 1D.
FIG. 1E shows a cross-sectional view of a completed semiconductor device having storage cell and peripheral circuit after the third photo-resist layer 32 is removed. In the drawing, it will be well known that a first polycrystalline silicon oxide layer 27 is thickly formed onto the side of the floating gate, referring to a cross-sectional view 36 in the direction of word line of the storage cell area 35. And it will be also clear that the floating and the control gates are formed in sequence in a bit-line direction, referring to a cross-section view 37 of the bit-line direction.
As understood from the foregoing description, when patterning of the floating gate is carried out after formation of the first polycrystalline silicon layer, the first silicon oxide layer 18 and the nitride layer 20, the O--N (Oxide-Nitride) layer itself alone formed of the silicon oxide layer 18 and nitride layer 20, is not enough to serve as a dielectric layer to block leakage current caused by electric charge retention or any electric field. Therefore, as shown in FIG. 1B, the O--N--O layer has to be completed by forming the second silicon oxide layer 26 on the nitride layer 20. At this time, the second silicon oxide layer 26 is formed not only on the top surface of the nitride layer 20 of the O--N insulation layer but also on the top surface of exposed silicon substrate of the peripheral circuit area, and is then formed to a thick silicon oxide layer on the side of the floating gate.
In consequence, thickness of the gate oxide layer 26 of the peripheral circuit area 40 cannot be properly controlled because the growth rate of the oxide layer is different between on the top surface of the nitride layer 20 of the storage cell area 35 and on the top surface of the exposed silicon substrate. That is, since the second silicon oxide layer 26 formed on the surface of the nitride layer 20 requires thickness of approximately 30 .ANG. to maintain a sufficiently even layer quality, a thick formation of a gate oxide layer having a thickness of more than at least 300 .ANG. is rendered on the surface of the exposed silicon substrate of the peripheral circuit area while the second silicon oxide layer is growing to such thickness. Accordingly, the prior art has a drawback that thickness of the gate oxide layer of the peripheral circuit area could hardly be controlled in order to obtain an optimum thickness for effective circuit operation.
Attempt to obtain the optimum thickness inevitably results in insufficient layer quality of the second oxide layer 26 on the surface of the nitride layer 20. As these days there has been a trend towards thinner gate oxide layer in MOS transistors, this drawback has led to further serious problem.
Meanwhile, when the second silicon oxide layer 20 is being formed, the polycrystalline silicon oxide layer 27, which is formed on the side of the floating gate 16, requires a thickness of more than 600 .ANG. in order to get an electric field strength that can be obtained from the insulation layer of O--N--O structure. To meet these conditions, a method of doping the first polycrystalline silicon layer with impurities has been typically employed.
Accordingly, since the first polycrystalline silicon oxide layer 27 is formed in a substantial thickness, the capacitance obtained at the side of the floating gate having the polycrystalline silicon oxide layer 27 as an insulator, can hardly contribute to increase of the total capacitance. Thereby, the capacitance obtained at the storage cell area will be limited to a capacitance that can be obtained at the planar area of the top surface of the floating gate.
That is, the more semiconductor devices are integrated, the more the planar area on the top surface of the floating gate is reduced, while the side area of the floating gate becomes larger. However, since the capacitance obtained at the storage cell area is limited to the capacitance that can be obtained at the planar area of the top surface of the floating gate, there is another drawback that sufficient capacitance for the optimum operation of a semiconductor device cannot be secured.